不同FPGA的不同管脚的电压有其特定的要求，所以必须查看器件说明书，并查看布局布线后产生的Fitter I/O报告中的All Package Report：
N.C.(No Connect) shows a pin that has no internal connection to the device.
VCCINTshows a dedicated power pin, which must be connected toVCCinternal signal.
VCCIOshows a dedicated power pin, which must be connected toVCCI/O bank.
VCC_PLLshows a dedicated power pin associated with ClockLock circuitry. This pin name appears only if the design contains aClockLock PLL.
GNDshows a dedicated ground pin or unused dedicated input, which must be connected toGND.
GND_PLLshows a dedicated ground pin associated with the ClockLock circuitry. This pin name appears only if the design contains a ClockLock PLL.
GNDINTshows a dedicated ground pin or unused dedicated input, which must be connected toGND internal signal.
GNDIOshows a dedicated ground pin which must be connected toGND.
RESERVEDshows an unused I/O pin, which must be left unconnected.
^character in nameshows a dedicated configuration pin.
+character in nameshows a reserved configuration pin that is tri-stated in user mode.
* character in name shows a reserved configuration pin that drives out in user mode.
# character in nameshows a JTAG BST/in-system programming or configuration pin. The JTAG inputsTMSandTDIshould be tied toVCC, andTCKshould be tied toGNDwhen not in use.
& character in nameshows a JTAG pin used as an I/O pin. When used as I/O pins, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
GND+shows an unused input. This pin should be connected toGND. It may also be connected to a legal signal on the board if that signal is required for a different revision of the design.
GND*shows an unused I/O pin that drives out