verilog_代码编写软件UE_高亮

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简介:今天有用UE查看verilog程序,下载的UE是破解版的,打开后灰蒙蒙的一片,很不爽的,于是搜索一番,下面是一段用于verilog在UE中高亮显示的程序,可以用的。以备后用。

1、代码保存成”.uew”文件放到UE的wordfiles文件夹下。这个wordfiles文件夹可以在UE的:高级/配置/编辑器显示/语法着色/文档完整目录名称中找到。如果找不到就是没有按照默认方式安装,那就查找吧。

2、在UE中按照路径:高级/配置/编辑器显示/语法着色/语言选择里面找到保存的uew文件点应用,确定就可以了。注意:如果找不到文件可以先把文档目录路径任意改一下,然后再改回来就可以了。

3、

/L14"Verilog 1364-2001" Line Comment = // Block Comment On = /* Block Comment Off = */ Block Comment On Alt = (* Block Comment Off Alt = *) String Chars = " File Extensions = V VL VMD

/Delimiters = ~!@%^&*()-+=|/{}[]:;"<> ,

/Function String = "%[ ^t]++^(config[ ^t^p]+[a-zA-Z0-9_]+^)"

/Function String 1 = "%[ ^t]++^(module[ ^t^p]+[a-zA-Z0-9_]+^)[ ^t^p]++[(;#]"

/Function String 2 = "%[ ^t]++^(task[ ^t^p]+[~(;]+^)[ ^t^p]++[(;#]"

/Function String 3 = "%[ ^t]++^(function[ ^t^p]+[~(;]+^)[ ^t^p]++[(;#]"

/Function String 4 = "%[ ^t]++^(primitive[ ^t^p]+[~(;]+^)[ ^t^p]++[(;#]"

/Function String 5 = "begin[ ^t^p]++^(:[ ^t^p]++[a-zA-Z0-9_]+^)"

/Indent Strings = "begin" "case" "fork" "specify" "table" "config"

/Unindent Strings = "end" "endcase" "join" "endspecify" "endtable" "endconfig"

/Open Fold Strings = "module" "task" "function" "generate" "primitive" "begin" "case" "fork" "specify" "table" "config" "`ifdef"

/Close Fold Strings = "endmodule" "endtask" "endfunction" "endgenerate" "endprimitive" "end" "endcase" "join" "endspecify" "endtable" "endconfig" "`endif"

/C1"Keywords"

always and assign automatic

begin buf bufif0 bufif1

case casex casez cell cmos config

deassign default defparam design disable

edge else end endcase endconfig endmodule endfunction endgenerate endprimitive endspecify endtable endtask event

for force forever fork function

generate genvar

highz0 highz1

if ifnone initial inout input instance integer

join

large liblist library localparam

macromodule medium module

nand negedge nmos none nor noshowcancelled not notif0 notif1

or output

parameter pulsestyle_onevent pulsestyle_ondetect pmos posedge primitive pull0 pull1 pullup pulldown

real realtime reg release repeat rcmos rnmos rpmos rtran rtranif0 rtanif1

scalared showcancelled signed small specify specparam strength strong0 strong1 supply0 supply1

table task time tran tranif0 tranif1 tri tri1 tri0 triand trior trireg

use

vectored

wait wand weak0 weak1 while wire wor

xnor xor

/C2"System"

** .

** 'b 'B 'o 'O 'd 'D 'h 'H 'sb 'sB 'so 'sO 'sd 'sD 'sh 'sH 'Sb 'SB 'So 'SO 'Sd 'SD 'Sh 'SH

** $

$async$and$array $async$and$plane $async$nand$array $async$nand$plane $async$nor$array $async$nor$plane $async$or$array $async$or$plane

$bitstoreal

$countdrivers

$display $displayb $displayh $displayo

$dist_chi_square $dist_erlang $dist_exponential $dist_normal $dist_poisson $dist_t $dist_uniform

$dumpall $dumpfile $dumpflush $dumplimit $dumpoff $dumpon $dumpportsall $dumpportsflush $dumpportslimit $dumpportsoff $dumpportson $dumpvars

$fclose $fdisplayh $fdisplay $fdisplayf $fdisplayb $ferror $fflush $fgetc $fgets $finish $fmonitorb $fmonitor $fmonitorf $fmonitorh $fopen $fread $fscanf $fseek $fsscanf $fstrobe $fstrobebb $fstrobef $fstrobeh $ftel $fullskew $fwriteb $fwritef $fwriteh $fwrite

$getpattern

$history $hold

$incsave $input $itor

$key

$list $log

$monitorb $monitorh $monitoroff $monitoron $monitor $monitoro

$nochange $nokey $nolog

$period $printtimescale

$q_add $q_exam $q_full $q_initialize $q_remove

$random $readmemb $readmemh $realtime $realtobits $recovery $recrem $removal $reset_count $reset $reset_value $restart $rewind $rtoi

$save $scale $scope $sdf_annotate $setup $setuphold $sformat $showscopes $showvariables $showvars $signed $skew $sreadmemb $sreadmemh $stime $stop $strobeb $strobe $strobeh $strobeo $swriteb $swriteh $swriteo $swrite $sync$and$array $sync$and$plane $sync$nand$array $sync$nand$plane $sync$nor$array $sync$nor$plane $sync$or$array $sync$or$plane

$test$plusargs $time $timeformat $timeskew

$ungetc $unsigned

$value$plusargs

$width $writeb $writeh $write $writeo

/C3"Operators"

!

%

&

*

+

,

-

// /

:

;

<

=

>

?

@

^

{

|

}

~

/C4"Directives"

** `

`accelerate `autoexepand_vectornets

`celldefine

`default_nettype `define `default_decay_time `default_trireg_strength `delay_mode_distributed `delay_mode_path `delay_mode_unit `delay_mode_zero

`else `elsif `endcelldefine `endif `endprotect `endprotected `expand_vectornets

`file

`ifdef `ifndef `include

`line

`noaccelerate `noexpand_vectornets `noremove_gatenames `noremove_netnames `nounconnected_drive

`protect `protected

`remove_gatenames `remove_netnames `resetall

`timescale

`unconnected_drive `undef `uselib

/C5"DelaysParametersEscaped"

#

**

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