基于51单片机can总线头文件定义

#include#include #include#define data_ora   P1                    //MCU P1<------> LCM#define uchar      unsigned char#define uint       unsigned int#define NOP _nop_()sbit req =P3^1;            //请求信号,H有效sbit busy=P3^0;            //H:已收到数据并在处理中,L:空闲可接收数据#define         SJA_PeliAdr       0x7f00        //定义sja1000的片选基址//计算SJA1000在电路中的实际地址:基址+内部寄存器地址#define         REG_MODE          XBYTE[SJA_PeliAdr+0x00]       //模式控制寄存器#define         REG_CMR        XBYTE[SJA_PeliAdr+0x01]       //命令寄存器#define         REG_SR           XBYTE[SJA_PeliAdr+0x02]       //状态寄存器#define         REG_IR        XBYTE[SJA_PeliAdr+0x03]       //中断寄存器#define         REG_IER        XBYTE[SJA_PeliAdr+0x04]       //中断使能寄存器#define         REG_BTR0          XBYTE[SJA_PeliAdr+0x06]       //总线定时寄存器0#define         REG_BTR1          XBYTE[SJA_PeliAdr+0x07]       //总线定时寄存器1#define         REG_OCR           XBYTE[SJA_PeliAdr+0x08]       //输出控制寄存器#define         REG_TEST          XBYTE[SJA_PeliAdr+0x09]       //测试寄存器#define         REG_ALC           XBYTE[SJA_PeliAdr+0x0B]       //仲裁丢失捕捉寄存器#define         REG_ECC           XBYTE[SJA_PeliAdr+0x0C]       //错误代码捕捉寄存器#define         REG_EWLR          XBYTE[SJA_PeliAdr+0x0D]       //错误报警限额寄存器#define         REG_RXERR         XBYTE[SJA_PeliAdr+0x0E]       //总线定时寄存器#define         REG_TXERR         XBYTE[SJA_PeliAdr+0x0F]       //输出控制寄存器#define         REG_ACR           XBYTE[SJA_PeliAdr+0x10]       //验收代码寄存器#define         REG_AMR           XBYTE[SJA_PeliAdr+0x14]       //验收屏蔽寄存器#define         REG_TXB           XBYTE[SJA_PeliAdr+0x10]       //发送缓冲区首址#define         REG_RXB           XBYTE[SJA_PeliAdr+0x10]       //接收缓冲区首址#define         REG_RMC           XBYTE[SJA_PeliAdr+0x1D]       //RX报文计数器寄存器#define         REG_RBSA          XBYTE[SJA_PeliAdr+0x1E]       //RX缓冲器起始地址寄存器#define         REG_CDR           XBYTE[SJA_PeliAdr+0x1F]       //时钟分频寄存器#define         REG_ACR0          XBYTE[SJA_PeliAdr+0x10]       //验收代码寄存器0#define         REG_ACR1          XBYTE[SJA_PeliAdr+0x11]       //验收代码寄存器1#define         REG_ACR2          XBYTE[SJA_PeliAdr+0x12]       //验收代码寄存器2#define         REG_ACR3          XBYTE[SJA_PeliAdr+0x13]       //验收代码寄存器3#define         REG_AMR0          XBYTE[SJA_PeliAdr+0x14]       //验收屏蔽寄存器0#define         REG_AMR1          XBYTE[SJA_PeliAdr+0x15]       //验收屏蔽寄存器1#define         REG_AMR2          XBYTE[SJA_PeliAdr+0x16]       //验收屏蔽寄存器2#define         REG_AMR3          XBYTE[SJA_PeliAdr+0x17]       //验收屏蔽寄存器3 //以下为发送缓冲区寄存器定义#define         REG_TxBuffer1     SJA_PeliAdr+0x10         //发送缓冲区1#define         REG_TxBuffer2     SJA_PeliAdr+0x11         //发送缓冲区2#define         REG_TxBuffer3     SJA_PeliAdr+0x12         //发送缓冲区3#define         REG_TxBuffer4     SJA_PeliAdr+0x13         //发送缓冲区4#define         REG_TxBuffer5     SJA_PeliAdr+0x14         //发送缓冲区5#define         REG_TxBuffer6     SJA_PeliAdr+0x15         //发送缓冲区6#define         REG_TxBuffer7     SJA_PeliAdr+0x16         //发送缓冲区7#define         REG_TxBuffer8     SJA_PeliAdr+0x17         //发送缓冲区8#define         REG_TxBuffer9     SJA_PeliAdr+0x18         //发送缓冲区9#define         REG_TxBuffer10    SJA_PeliAdr+0x19         //发送缓冲区10//以下为接收缓冲区寄存器定义#define         REG_RxBuffer1     SJA_PeliAdr+0x14         //接收缓冲区1#define         REG_RxBuffer2     SJA_PeliAdr+0x15         //接收缓冲区2#define         REG_RxBuffer3     SJA_PeliAdr+0x16         //接收缓冲区3#define         REG_RxBuffer4     SJA_PeliAdr+0x17         //接收缓冲区4#define         REG_RxBuffer5     SJA_PeliAdr+0x18         //接收缓冲区5#define         REG_RxBuffer6     SJA_PeliAdr+0x19         //接收缓冲区6#define         REG_RxBuffer7     SJA_PeliAdr+0x1A         //接收缓冲区7#define         REG_RxBuffer8     SJA_PeliAdr+0x1B         //接收缓冲区8#define         REG_RxBuffer9     SJA_PeliAdr+0x1C         //接收缓冲区9#define         REG_RxBuffer10    SJA_PeliAdr+0x1D         //接收缓冲区10 uchar xdata  *SJA_PeliCANAdr;   #define         TR_CMD           0x01          //发送请求命令#define         AT_CMD           0x02          //夭折发送命令#define         RRB_CMD          0x04          //释放接收缓冲区#define         COS_CMD          0x08          //清除超载状态#define         GTS_CMD          0x10          //进入睡眠状态命令 #define         ByteRate_20k      0x00          //波特率20kbps#define         ByteRate_40k      0x01          //波特率40kbps#define         ByteRate_50k      0x02          //波特率50kbps#define         ByteRate_80k      0x03          //波特率80kbps#define         ByteRate_100k     0x04          //波特率100kbps#define         ByteRate_125k     0x05          //波特率125kbps#define         ByteRate_200k     0x06          //波特率200kbps#define         ByteRate_250k     0x07          //波特率250kbps#define         ByteRate_400k     0x08          //波特率400kbps#define         ByteRate_500k     0x09          //波特率500kbps#define         ByteRate_666k     0x0a          //波特率666kbps#define         ByteRate_800k     0x0b          //波特率800kbps#define         ByteRate_1000k    0x0c          //波特率1000kbps#define         IDADDR     XBYTE[0xbf00]    //74LS244地址，用于确定节点号uchar data SJA_TXBuffer[13]={0x88,0x33,0x33,0x33,0x33,0x33,0x33,0x33,0x33,0x33,0x33,0x33,0x33};bit RX_OK=0;void SJA_Init_Peli(void) {  REG_MODE=0X01;  REG_CDR =0X80;  REG_IER =0X0D;  REG_AMR0=0XFF;  REG_AMR1=0XFF;  REG_AMR2=0XFF;  REG_AMR3=0XFF;  REG_ACR0=0X00;  REG_ACR1=0XFF;  REG_ACR2=IDADDR & 0x0f;  REG_ACR3=0X00;  REG_BTR0=0X40;  REG_BTR1=0X1C;  REG_OCR =0XAA;  REG_RBSA=0X00;  REG_TXERR=0X00;  REG_ECC =0X00;  REG_MODE=0X00; }void SJA_TX_Peli(void) {  uchar a,i;  a=REG_SR;  if(a&0x10)   {    a=REG_SR;   }  if(!(a&0x08))   {    a=REG_SR;   }  if(!(a&0x04))   {    a=REG_SR;   }  SJA_PeliCANAdr=REG_TXB;  a=SJA_TXBuffer[0];  a&=0x0f;  a=a+4;   *SJA_PeliCANAdr=SJA_TXBuffer[0];  for(i=0;i    {    SJA_PeliCANAdr++;    *SJA_PeliCANAdr=SJA_TXBuffer[i+1];   }  REG_CMR=0X01; }void SJA_RX_Peli(void) {  uchar bdata a,b,i;  a=REG_SR;  if(a&0xC3)   {    if(a&0x80)     {      b=REG_IR;      REG_MODE=0X00;      return;     }    else     {       b=REG_IR;       if(b&0X08)        {        REG_CMR=0X0C;        return;       }             else       {        if(b&0X01)         {          SJA_PeliCANAdr=REG_TXB;          SJA_TXBuffer[0]=*SJA_PeliCANAdr;          a=SJA_TXBuffer[0];          a&=0x0f;          a=a+4;          for(i=0;i            {            SJA_PeliCANAdr++;            SJA_TXBuffer[i+1]=*SJA_PeliCANAdr;           }          RX_OK=1;          REG_CMR=0X04;         }        a=REG_ALC;        a=REG_ECC;        return;               }      }   }  else   {    return;   }       }void main(void) {   uchar i=0;  SP=0x60;  SJA_Init_Peli();  SJA_TX_Peli();  while(i!=0XC8)   {    SJA_RX_Peli();    if(RX_OK)     {      i++;      RX_OK=0;     }   }  SJA_TX_Peli();  while(1); }